EZ80L92MCU Datasheet, PDF (121/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
106
edge of the RxD input start bit. It then receives a complete byte according to the set
parameters. The receiver also implements logic to detect framing errors, parity errors,
overrun errors, and break signals.
UART Modem Control
The modem control logic provides two outputs and four inputs for handshaking with the
modem. Any change in the modem status inputs, except RI, is detected and an interrupt
can be generated. For RI, an interrupt is generated only when the trailing edge of the RI is
detected. The module also provides LOOP mode for self-diagnostics.
UART Interrupts
There are five different sources of interrupts from the UART. The five sources of inter-
rupts are:
• Transmitter
• Receiver (three different interrupts)
• Modem status
UART Transmitter Interrupt
The transmitter interrupt is generated if there is no data available for transmission. This
interrupt can be disabled using the individual interrupt enable bit or cleared by writing
data into the UARTx_THR register.
UART Receiver Interrupts
A receiver interrupt can be generated by three possible sources. The first source, a receiver
data ready, indicates that one or more data bytes are received and are ready to be read.
This interrupt is generated if the number of bytes in the receiver FIFO is greater than or
equal to the trigger level. If the FIFO is not enabled, the interrupt is generated if the
receive buffer contains a data byte. This interrupt is cleared by reading the UARTx_RBR.
The second interrupt source is the receiver time-out. A receiver time-out interrupt is gener-
ated when there are fewer data bytes in the receiver FIFO than the trigger level and there
are no Reads and Writes to or from the receiver FIFO for four consecutive byte times.
When the receiver time-out interrupt is generated, it is cleared only after emptying the
entire receive FIFO.
The first two interrupt sources from the receiver (data ready and time-out) share an inter-
rupt enable bit.
The third source of a receiver interrupt is a line status error, indicating an error in byte
reception. This error may result from:
• Incorrect received parity
PS013012-1004
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter