EZ80L92MCU Datasheet, PDF (158/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
143
• A repeated START condition and a data bit
• A STOP condition and a data bit
• A repeated START condition and a STOP condition
Clock Synchronization for Handshake
The Clock synchronizing mechanism can function as a handshake, enabling receivers to
cope with fast data transfers, on either a byte or bit level. The byte level allows a device to
receive a byte of data at a fast rate, but allows the device more time to store the received
byte or to prepare another byte for transmission. Slaves hold the SCL line Low after
reception and acknowledge the byte, forcing the master into a wait state until the slave is
ready for the next byte transfer in a handshake procedure.
Operating Modes
Master Transmit
In MASTER TRANSMIT mode, the I²C transmits a number of bytes to a slave receiver.
Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register to 1.
The I²C then tests the I²C bus and transmits a START condition when the bus is free.
When a START condition is transmitted, the IFLG bit is 1 and the status code in the
I2C_SR register is 08h. Before this interrupt is serviced, the I2C_DR register must be
loaded with either a 7-bit slave address or the first part of a 10-bit slave address, with the
lsb cleared to 0 to specify TRANSMIT mode. The IFLG bit should now be cleared to 0 to
prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit are
transmitted, the IFLG is set again. A number of status codes are possible in the I2C_SR
register. See Table 75.
PS013012-1004
PRELIMINARY
I²C Serial I/O Interface