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EZ80L92MCU Datasheet, PDF (223/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers
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eZ80L92 MCU
Product Specification
208
External I/O Read Timing
Figure 51 and Table 131 diagram the timing for external I/O Reads.
X IN
ADDR[23:0]
TCLK
T1
DATA[7:0]
(input)
CSx
IORQ
RD
T5
T7
T9
Figure 51. External I/O Read Timing
T2
T3
T4
T6
T8
T10
Table 131. External I/O Read Timing
Parameter Abbreviation
T1
Clock Rise to ADDR Valid Delay
T2
Clock Rise to ADDR Hold Time
T3
Input DATA Valid to Clock Rise Setup Time
T4
Clock Rise to DATA Hold Time
T5
Clock Rise to CSx Assertion Delay
T6
Clock Rise to CSx Deassertion Delay
T7
Clock Rise to IORQ Assertion Delay
T8
Clock Rise to IORQ Deassertion Delay
20 MHz (ns)
Min
—
2.2
0.4
1.3
2.6
2.4
2.6
2.3
Max
6.9
—
—
—
10.8
8.8
7.0
6.3
50 MHz (ns)
Min.
—
2.2
0.4
1.3
2.6
2.4
2.6
2.3
Max.
6.9
—
—
—
10.8
8.8
7.0
6.3
PS013012-1004
PRELIMINARY
AC Characteristics
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