EZ80L92MCU Datasheet, PDF (185/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
170
Table 93. ZDI Break Control Register (ZDI_BRK_CTL = 10h in the ZDI Write-Only
Register Address Space)
Bit
Reset
CPU Access
Note: W = Write-only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Bit
Position
7
BRK_NEXT
6
brk_addr3
5
brk_addr2
4
brk_addr1
3
brk_addr0
Value Description
0
The ZDI BREAK on the next CPU instruction is disabled.
Clearing this bit releases the CPU from its current BREAK
condition.
1
The ZDI BREAK on the next CPU instruction is enabled.
The CPU can use multibyte Op Codes and multibyte
operands. break points only occur on the first Op Code in
a multibyte Op Code instruction. If the ZCL pin is High and
the ZDA pin is Low at the end of RESET, this bit is set to 1
and a BREAK occurs on the first instruction following the
RESET. This bit is set automatically during ZDI BREAK
on address match. A BREAK can also be forced by
writing a 1 to this bit.
0
The ZDI BREAK, upon matching break address 3, is
disabled.
1
The ZDI BREAK, upon matching break address 3, is
enabled.
0
The ZDI BREAK, upon matching break address 2, is
disabled.
1
The ZDI BREAK, upon matching break address 2, is
enabled.
0
The ZDI BREAK, upon matching break address 1, is
disabled.
1
The ZDI BREAK, upon matching break address 1, is
enabled.
0
The ZDI BREAK, upon matching break address 0, is
disabled.
1
The ZDI BREAK, upon matching break address 0, is
enabled.
PS013012-1004
PRELIMINARY
ZiLOG Debug Interface