EZ80L92MCU Datasheet, PDF (21/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
6
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued)
Pin #
7
8
9
Symbol
V_DD
V_SS
ADDR6
Function
Signal Direction
Power Supply
Ground
Address Bus Bidirectional
10 ADDR7 Address Bus Bidirectional
11 ADDR8 Address Bus Bidirectional
12 ADDR9 Address Bus Bidirectional
13 ADDR10 Address Bus Bidirectional
Description
Power Supply.
Ground.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
PS013012-1004
PRELIMINARY
Architectural Overview