EZ80L92MCU Datasheet, PDF (22/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
7
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued)
Pin # Symbol
14 ADDR11
Function
Signal Direction
Address Bus Bidirectional
15 ADDR12 Address Bus Bidirectional
16 ADDR13 Address Bus Bidirectional
17 ADDR14 Address Bus Bidirectional
18
V_DD
Power Supply
19
V_SS
Ground
20 ADDR15 Address Bus Bidirectional
Description
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Power Supply.
Ground.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
PS013012-1004
PRELIMINARY
Architectural Overview