EZ80L92MCU Datasheet, PDF (43/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
28
Table 3. Register Map (Continued)
Address
(hex) Mnemonic
Name
Reset
(hex)
CPU Page
Access #
Chip Select/Wait State Generator
00B2 CS3_UBR
Chip Select 3 Upper Bound Register
00
R/W
68
00B3 CS3_CTL
Chip Select 3 Control Register
00
R/W
69
Serial Peripheral Interface (SPI) Block
00B8 SPI_BRG_L
SPI Baud Rate Generator Register—Low
02
Byte
R/W
133
00B9 SPI_BRG_H
SPI Baud Rate Generator Register—High
00
Byte
00BA SPI_CTL
SPI Control Register
04
00BB SPI_SR
SPI Status Register
00
00BC SPI_TSR
SPI Transmit Shift Register
XX
SPI_RBR
SPI Receive Buffer Register
XX
Infrared Encoder/Decoder Block
00BF IR_CTL
Infrared Encoder/Decoder Control
00
R/W
133
R/W
134
R
135
W
136
R
137
R/W
125
Universal Asynchronous Receiver/Transmitter 0 (UART0) Block
00C0 UART0_RBR UART 0 Receive Buffer Register
XX
R
111
UART0_THR UART 0 Transmit Holding Register
XX
W
111
UART0_BRG_L UART 0 Baud Rate Generator Register— 02
Low Byte
R/W
110
00C1 UART0_IER
UART 0 Interrupt Enable Register
00
R/W
112
UART0_BRG_H UART 0 Baud Rate Generator Register— 00
High Byte
R/W
110
00C2 UART0_IIR
UART 0 Interrupt Identification Register
01
R
113
UART0_FCTL UART 0 FIFO Control Register
00
W
114
00C3 UART0_LCTL UART 0 Line Control Register
00
R/W
115
Notes:
1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-
out reset, the Watch-Dog Timer Control register is reset to 20h.
2. When the CPU reads this register, the current sampled value of the port is read.
3. Read-only if RTC is locked; Read/Write if RTC is unlocked.
4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm
Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
PS013012-1004
PRELIMINARY
Register Map