EZ80L92MCU Datasheet, PDF (51/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
36
• eZ80^® CPU is idle
• Program counter (PC) stops incrementing
The eZ80^® CPU can be brought out of HALT mode by any of the following operations:
• Nonmaskable interrupt (NMI)
• Maskable interrupt
• RESET via the external RESET pin driven Low
• Watch-Dog Timer time-out (if configured to generate either an NMI or RESET upon
time-out)
• RESET via execution of a Debug RESET command
To minimize current in HALT mode, the system clock should be disabled for all unused
on-chip peripherals via the Clock Peripheral Power-Down Registers.
Clock Peripheral Power-Down Registers
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be disabled to unused on-chip peripherals. Upon RESET, all peripherals are enabled. The
clock to unused peripherals can be disabled by setting the appropriate bit in the Clock
Peripheral Power-Down Registers to 1. When powered down, the peripherals are com-
pletely disabled. To reenable, the bit in the Clock Peripheral Power-Down Registers must
be cleared to 0.
Many peripherals feature separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
down, the standard peripheral control registers are not accessible for Read or Write access.
See Tables 4 and 5.
PS013012-1004
PRELIMINARY
Low-Power Modes