EZ80L92MCU Datasheet, PDF (72/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
57
Table 16. Intel™ Bus Mode Read States (Separate Address and Data Buses)
STATE T3
STATE T4
During State T3, no bus signals are altered. If the external ReadY (WAIT)
pin is driven Low at least one eZ80^® system clock cycle prior to the
beginning of State T3, additional WAIT states (T_WAIT) are asserted until
the ReadY pin is driven High.
The CPU latches the Read data at the beginning of State T4. The CPU
deasserts the RD signal and completes the Intel Bus Mode cycle.
During Write operations with separate address and data buses, the Intel Bus Mode
employs 4 states (T1, T2, T3, and T4) as described in Table 17.
Table 17. Intel™ Bus Mode Write States (Separate Address and Data Buses)
STATE T1
STATE T2
STATE T3
STATE T4
The Write cycle begins in State T1. The CPU drives the address onto the
address bus, the associated Chip Select signal is asserted, and the data
is driven onto the data bus. The CPU drives the ALE signal High at the
beginning of T1. During the middle of T1, the CPU drives ALE Low to
facilitate the latching of the address.
During State T2, the CPU asserts the WR signal. Depending on the
instruction, either the MREQ or IORQ signal is asserted.
During State T3, no bus signals are altered. If the external ReadY (WAIT)
pin is driven Low at least one eZ80^® system clock cycle prior to the
beginning of State T3, additional WAIT states (T_WAIT) are asserted until
the ReadY pin is driven High.
The CPU deasserts the WR signal at the beginning of State T4. The CPU
holds the data and address buses through the end of T4. The bus cycle is
completed at the end of T4.
Intel Bus Mode timing is illustrated for a Read operation in Figure 10 and for a Write
operation in Figure 11. If the ReadY signal (external WAIT pin) is driven Low prior to the
beginning of State T3, additional WAIT states
is driven High. The Intel Bus Mode states can
(T_WAIT) are asserted until
be configured for 2 to 15
the ReadY signal
eZ80^® system
clock cycles. In the figures, each Intel™ Bus Mode state is 2 eZ80^® system clock cycles
in duration. Figures 10 and 11 also illustrate the assertion of one WAIT state (T_WAIT) by
the selected peripheral.
PS013012-1004
PRELIMINARY
Chip Selects and Wait States