EZ80L92MCU Datasheet, PDF (85/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
70
Chip Select x Bus Mode Control Registers
The Chip Select Bus Mode register, detailed in Table 25, configures the Chip Select for
eZ80^®, Z80, Intel™, or Motorola Bus Modes. Changing the bus mode allows the
eZ80L92 to interface to peripherals based on the Z80-, Intel™-, or Motorola-style asyn-
chronous bus interfaces. When a bus mode other than eZ80^® is programmed for a particu-
lar Chip Select, the CSx_WAIT setting in that Chip Select Control Register is ignored.
Table 25. Chip Select x Bus Mode Control Registers (CS0_BMC = 00F0h, CS1_BMC
= 00F1h, CS2_BMC = 00F2h, CS3_BMC = 00F3h)
Bit
7
6
5
4
3
2
1
0
CS0_BMC Reset
0
0
0
0
0
0
1
0
CS1_BMC Reset
0
0
0
0
0
0
1
0
CS2_BMC Reset
0
0
0
0
0
0
1
0
CS3_BMC Reset
0
0
0
0
0
0
1
0
CPU Access
R/W R/W R/W R R/W R/W R/W R/W
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:6]
BUS_MODE
5
AD_MUX
4
Value Description
00
eZ80^® bus mode.
01 Z80 bus mode.
10 Intel™ bus mode.
11 Motorola bus mode.
0
Separate address and data.
1
Multiplexed address and data—appears on data bus
DATA[7:0].
0
Reserved.
PS013012-1004
PRELIMINARY
Chip Selects and Wait States