EZ80L92MCU Datasheet, PDF (145/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
130
Table 68. SPI Clock Phase and Clock Polarity Operation
CPHA
1
1
CPOL
0
1
SCK
Transmit
Edge
Rising
Falling
SCK
Receive
Edge
Falling
Rising
SCK
Idle
State
Low
High
SS High
Between
Characters?
No
No
SPI Functional Description
When a master transmits to a slave device via the MOSI signal, the slave device responds
by sending data to the master via the master's MISO signal. The resulting implication is a
full-duplex transmission, with both data out and data in synchronized with the same clock
signal. Thus the byte transmitted is replaced by the byte received and eliminates the
requirement for separate transmit-empty and receive-full status bits. A single status bit,
SPIF, is used to signify that the I/O operation is completed, see the SPI Status Register
(SPI_SR) on page 135.
The SPI is double-buffered on Read, but not on Write. If a Write is performed during data
transfer, the transfer occurs uninterrupted, and the Write is unsuccessful. This condition
causes the WRITE COLLISION (WCOL) status bit in the SPI_SR register to be set. After
a data byte is shifted, the SPIF flag of the SPI_SR register is set.
In SPI MASTER mode, the SCK pin is an output. It idles High or Low, depending on the
CPOL bit in the SPI_CTL register, until data is written to the shift register. Data transfer is
initiated by writing to the transmit shift register, SPI_TSR. Eight clocks are then generated
to shift the eight bits of transmit data out the MOSI pin while shifting in eight bits of data
on the MISO pin. After transfer, the SCK signal idles.
In SPI SLAVE mode, the start logic receives a logic Low from the SS pin and a clock
input at the SCK pin, and the slave is synchronized to the master. Data from the master is
received serially from the slave MOSI signal and loads the 8-bit shift register. After the 8-
bit shift register is loaded, its data is parallel transferred to the Read buffer. During a Write
cycle data is written into the shift register, then the slave waits for the SPI master to ini-
tiate a data transfer, supply a clock signal, and shift the data out on the slave's MISO sig-
nal.
If the CPHA bit in the SPI_CTL register is 0, a transfer begins when SS pin signal goes
Low and the transfer ends when SS goes High after eight clock cycles on SCK. When the
CPHA bit is set to 1, a transfer begins the first time SCK becomes active while SS is Low
and the transfer ends when the SPIF flag gets set.
PS013012-1004
PRELIMINARY
Serial Peripheral Interface