EZ80L92MCU Datasheet, PDF (62/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
47
Table 12. Vectored Interrupt Operation (Continued)
Memory
Mode
Z80 Mode
ADL
Bit
0
ADL Mode 1
MADL
Bit Operation
1
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT[7:0], bus by the interrupting peripheral.
• IEF1 ← 0
• IEF2 ← 0
• The starting Program Counter is effectively {MBASE, PC[15:0]}.
• Push the 2-byte return address, PC[15:0], onto the SPL stack.
• Push a 00h byte onto the SPL stack to indicate an interrupt from Z80
mode (because ADL = 0).
• Set the ADL mode bit to 1.
• The interrupt vector address is located at { 00h, I[7:0], IVECT[7:0] }.
• PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
• The ending Program Counter is { 00h, PC[15:0] }.
• The interrupt service routine must end with RETI.L
1
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
• IEF1 ← 0
• IEF2 ← 0
• The starting Program Counter is PC[23:0].
• Push the 3-byte return address, PC[23:0], onto the SPL stack.
• Push a 01h byte onto the SPL stack to indicate a restart from ADL mode
(because ADL = 1).
• The ADL mode bit remains set to 1.
• The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]}.
• PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
• The ending Program Counter is { 00h, PC[15:0] }.
• The interrupt service routine must end with RETI.L
Nonmaskable Interrupts
An active Low input on the NMI pin generates an interrupt request to the eZ80^® CPU.
This nonmaskable interrupt is always serviced by the eZ80^® CPU, regardless of the state
of the Interrupt Enable flags (IEF1 and IEF2). The nonmaskable interrupt is prioritized
higher than all maskable interrupts. The response of the eZ80^® CPU to a nonmaskable
interrupt is described in detail in the eZ80^® CPU User Manual (UM0077).
PS013012-1004
PRELIMINARY
Interrupt Controller