EZ80L92MCU Datasheet, PDF (206/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
191
Op-Code Map
Tables 118 through 124 indicate the hex values for each of the eZ80^® instructions.
Table 118. Op Code Map—First Op Code
Legend
Lower Op Code Nibble
Upper
Op Code
Nibble
4
A
AND
A,H
Mnemonic
First Operand
Second Operand
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
0 NOP
LD
BC,
Mmn
LD
(BC),A
INC
BC
1
DJNZ
d
LD
DE,
Mmn
LD
(DE),A
INC
DE
2
JR
NZ,d
LD
LD
HL, (Mmn),
Mmn HL
INC
HL
3
JR
NC,d
LD
LD
SP, (Mmn),
Mmn
A
INC
SP
INC
B
DEC
B
LD
B,n
RLCA
EX
AF,AF’
ADD
HL,BC
LD
A,(BC)
DEC
BC
INC DEC LD
D
D
D,n
RLA
JR ADD LD DEC
d HL,DE A,(DE) DE
INC
H
DEC
H
LD
H,n
DAA
JR
Z,d
ADD
HL,HL
LD
HL,
(Mmn)
DEC
HL
INC
(HL)
DEC
(HL)
LD
(HL),n
SCF
JR
CF,d
ADD
HL,SP
LD
A,
(Mmn)
DEC
SP
4
.SIS
suffix
LD
B,C
LD
B,D
LD
B,E
LD
B,H
LD
LD
LD
B,L B,(HL) B,A
LD .LIS LD
C,B suffix C,D
LD
C,E
5
LD
D,B
LD .SIL LD
D,C suffix D,E
LD
D,H
LD
LD
LD
D,L D,(HL) D,A
LD
E,B
LD
E,C
LD .LIL
E,D suffix
6
LD
H,B
LD
LD
LD
H,C H,D H,E
LD
H,H
LD
LD
LD
H,L H,(HL) H,A
LD
L,B
LD
L,C
LD
L,D
LD
L,E
7
LD
(HL),B
LD
(HL),C
LD
(HL),D
LD
(HL),E
LD
(HL),H
LD
(HL),L
HALT
LD
(HL),A
LD
A,B
LD
A,C
LD
A,D
LD
A,E
8
ADD
A,B
ADD
A,C
ADD
A,D
ADD
A,E
ADD
A,H
ADD ADD ADD
A,L A,(HL) A,A
ADC
A,B
ADC
A,C
ADC
A,D
ADC
A,E
9
SUB
A,B
SUB
A,C
SUB
A,D
SUB
A,E
SUB
A,H
SUB SUB SUB
A,L A,(HL) A,A
SBC
A,B
SBC
A,C
SBC
A,D
SBC
A,E
A
AND
A,B
AND
A,C
AND
A,D
AND
A,E
AND
A,H
AND AND AND
A,L A,(HL) A,A
XOR
A,B
XOR
A,C
XOR
A,D
XOR
A,E
B
OR
A,B
OR
A,C
OR
A,D
OR
A,E
OR
A,H
OR OR OR
A,L A,(HL) A,A
CP
A,B
CP
A,C
CP
A,D
CP
A,E
C
RET
NZ
D
RET
NC
E
RET
PO
F
RET
P
POP
BC
POP
DE
POP
HL
POP
AF
JP
NZ,
Mmn
JP
NC,
Mmn
JP
PO,
Mmn
JP
P,
Mmn
JP
Mmn
OUT
(n),A
EX
(SP),HL
DI
CALL
NZ,
Mmn
CALL
NC,
Mmn
CALL
PO,
Mmn
CALL
P,
Mmn
PUSH
BC
PUSH
DE
PUSH
HL
PUSH
AF
ADD
A,n
SUB
A,n
AND
A,n
OR
A,n
RST
00h
RST
10h
RST
20h
RST
30h
RET
Z
RET
CF
RET
PE
RET
M
RET
EXX
JP
(HL)
LD
SP,HL
JP
Z,
Mmn
JP
CF,
Mmn
JP
PE,
Mmn
JP
M,
Mmn
Table
119
IN
A,(n)
EX
DE,HL
EI
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
C
INC
C
INC
E
INC
L
INC
A
LD
C,H
LD
E,H
LD
L,H
LD
A,H
ADC
A,H
SBC
A,H
XOR
A,H
CP
A,H
CALL
Z,
Mmn
CALL
CF,
Mmn
CALL
PE,
Mmn
CALL
M,
Mmn
D
DEC
C
DEC
E
DEC
L
DEC
A
LD
C,L
LD
E,L
LD
L,L
LD
A,L
ADC
A,L
SBC
A,L
XOR
A,L
CP
A,L
CALL
Mmn
Table
120
Table
121
Table
122
E
F
LD
C,n
RRCA
LD
E,n
RRA
LD
L,n
CPL
LD
A,n
LD
C,(HL)
LD
E,(HL)
LD
L,(HL)
LD
A,(HL)
ADC
A,(HL)
SBC
A,(HL)
XOR
A,(HL)
CP
A,(HL)
ADC
A,n
CCF
LD
C,A
LD
E,A
LD
L,A
LD
A,A
ADC
A,A
SBC
A,A
XOR
A,A
CP
A,A
RST
08h
SBC RST
A,n 18h
XOR RST
A,n 28h
CP RST
A,n 38h
PS013012-1004
PRELIMINARY
Op-Code Map