EZ80L92MCU Datasheet, PDF (61/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
46
{MBASE[7:0], I[7:0], 1Eh} and {MBASE, I[7:0], 1Fh}. The least significant byte is
stored at the lower address.
When any one or more of the interrupt requests (IRQs) become active, an interrupt request
is generated by the interrupt controller and sent to the CPU. The corresponding 8-bit inter-
rupt vector for the highest priority interrupt is placed on the 8-bit interrupt vector bus,
IVECT[7:0]. The interrupt vector bus is internal to the eZ80L92 and is therefore not visi-
ble externally. The response time of the eZ80^® CPU to an interrupt request is a function of
the current instruction being executed as well as the number of WAIT states being
asserted. The interrupt vector, {I[7:0], IVECT[7:0]}, is visible on the address bus,
ADDR[15:0], when the interrupt service routine begins. The response of the eZ80^® CPU
to a vectored interrupt on the eZ80L92 is explained in Table 12. Interrupt sources are
required to be active until the Interrupt Service Routine (ISR) starts. It is recommended
that the Interrupt Page Address Register (I) value be changed by the user from its default
value of 00h as this address can create conflicts between the nonmaskable interrupt vector,
the RST instruction addresses, and the maskable interrupt vectors.
Table 12. Vectored Interrupt Operation
Memory
Mode
Z80 Mode
ADL
Bit
0
ADL Mode 1
MADL
Bit Operation
0
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
• IEF1 ← 0
• IEF2 ← 0
• The starting Program Counter is effectively {MBASE, PC[15:0]}.
• Push the 2-byte return address PC[15:0] onto the ({MBASE,SPS}) stack.
• The ADL mode bit remains cleared to 0.
• The interrupt vector address is located at { MBASE, I[7:0], IVECT[7:0] }.
• PC[15:0] ← ( { MBASE, I[7:0], IVECT[7:0] } ).
• The ending Program Counter is effectively {MBASE, PC[15:0]}
• The interrupt service routine must end with RETI.
0
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
• IEF1 ← 0
• IEF2 ← 0
• The starting Program Counter is PC[23:0].
• Push the 3-byte return address, PC[23:0], onto the SPL stack.
• The ADL mode bit remains set to 1.
• The interrupt vector address is located at { 00h, I[7:0], IVECT[7:0] }.
• PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
• The ending Program Counter is { 00h, PC[15:0] }.
• The interrupt service routine must end with RETI.
PS013012-1004
PRELIMINARY
Interrupt Controller