EZ80L92MCU Datasheet, PDF (24/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
9
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued)
Pin # Symbol
27 ADDR22
28 ADDR23
29 CS0
30 CS1
31 CS2
32 CS3
33
V_DD
34
V_SS
35 DATA0
36 DATA1
Function
Signal Direction
Address Bus Bidirectional
Address Bus Bidirectional
Chip Select 0 Output, Active Low
Chip Select 1 Output, Active Low
Chip Select 2 Output, Active Low
Chip Select 3 Output, Active Low
Power Supply
Ground
Data Bus
Bidirectional
Data Bus
Bidirectional
Description
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
CS0 Low indicates that an access is
occurring in the defined CS0 memory or I/
O address space.
CS1 Low indicates that an access is
occurring in the defined CS1 memory or I/
O address space.
CS2 Low indicates that an access is
occurring in the defined CS2 memory or I/
O address space.
CS3 Low indicates that an access is
occurring in the defined CS3 memory or I/
O address space.
Power Supply.
Ground.
The data bus transfers data to and from I/O
and memory devices. The eZ80L92 MCU
drives these lines only during Write cycles
when the eZ80L92 MCU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The eZ80L92 MCU
drives these lines only during Write cycles
when the eZ80L92 MCU is the bus master.
PS013012-1004
PRELIMINARY
Architectural Overview