EZ80L92MCU Datasheet, PDF (89/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
74
determine the source of the NMI event, provided that the last RESET was not caused by
the WDT.
Watch-Dog Timer Registers
Watch-Dog Timer Control Register
The Watch-Dog Timer Control register, detailed in Table 27, is an 8-bit Read/Write regis-
ter used to enable the Watch-Dog Timer, set the time-out period, indicate the source of the
most recent RESET, and select the required operation upon WDT time-out.
Table 27. Watch-Dog Timer Control Register (WDT_CTL = 0093h)
Bit
7
6
5
4
3
2
1
0
Reset
0
0
0/1
0
0
0
0
0
CPU Access
R/W R/W R R/W R/W R R/W R/W
Note: R = Read only; R/W = Read/Write.
Bit
Position
Value Description
7
WDT_EN
0
WDT is disabled.
1
WDT is enabled. When enabled, the WDT cannot be disabled
without a full RESET.
6
NMI_OUT
0
WDT time-out resets the CPU.
1
WDT time-out generates a nonmaskable interrupt (NMI) to the
CPU.
5
0
RST_FLAG^*
1
RESET caused by external full-chip reset or ZDI reset.
RESET caused by WDT time-out. This flag is set by the WDT
time-out, even if the NMI_OUT flag is set to 1. The CPU can
poll this bit to determine the source of the RESET or NMI.
[4:3]
WDT_CLK
00 WDT clock source is system clock.
01 WDT clock source is Real-Time Clock source (32KHz on-chip
oscillator or 50/60Hz input as set by RTC_CTRL[4]) .
10 Reserved.
11 Reserved.
2
0
RESERVED
Reserved.
Note: *RST_FLAG is only cleared by a non-WDT RESET.
PS013012-1004
PRELIMINARY
Watch-Dog Timer