EZ80L92MCU Datasheet, PDF (42/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
27
Table 3. Register Map (Continued)
Address
(hex) Mnemonic
Name
General-Purpose Input/Output Ports
009A PB_DR
Port B Data Register²
009B PB_DDR
Port B Data Direction Register
009C PB_ALT1
Port B Alternate Register 1
009D PB_ALT2
Port B Alternate Register 2
009E PC_DR
Port C Data Register
009F PC_DDR
Port C Data Direction Register
00A0 PC_ALT1
Port C Alternate Register 1
00A1 PC_ALT2
Port C Alternate Register 2
00A2 PD_DR
Port D Data Register
00A3 PD_DDR
Port D Data Direction Register
00A4 PD_ALT1
Port D Alternate Register 1
00A5 PD_ALT2
Port D Alternate Register 2
Reset
(hex)
CPU Page
Access #
XX
R/W
43
FF
R/W
44
00
R/W
44
00
R/W
44
XX
R/W²
43
FF
R/W
44
00
R/W
44
00
R/W
44
XX
R/W²
43
FF
R/W
44
00
R/W
44
00
R/W
44
Chip Select/Wait State Generator
00A8 CS0_LBR
Chip Select 0 Lower Bound Register
00
R/W
67
00A9 CS0_UBR
Chip Select 0 Upper Bound Register
FF
R/W
68
00AA CS0_CTL
Chip Select 0 Control Register
E8
R/W
69
00AB CS1_LBR
Chip Select 1 Lower Bound Register
00
R/W
67
00AC CS1_UBR
Chip Select 1 Upper Bound Register
00
R/W
68
00AD CS1_CTL
Chip Select 1 Control Register
00
R/W
69
00AE CS2_LBR
Chip Select 2 Lower Bound Register
00
R/W
67
00AF CS2_UBR
Chip Select 2 Upper Bound Register
00
R/W
68
00B0 CS2_CTL
Chip Select 2 Control Register
00
R/W
69
00B1 CS3_LBR
Chip Select 3 Lower Bound Register
00
R/W
67
Notes:
1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-
out reset, the Watch-Dog Timer Control register is reset to 20h.
2. When the CPU reads this register, the current sampled value of the port is read.
3. Read-only if RTC is locked; Read/Write if RTC is unlocked.
4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm
Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
PS013012-1004
PRELIMINARY
Register Map