EZ80L92MCU Datasheet, PDF (225/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
210
Table 132. External I/O Write Timing
20 MHz (ns)
50 MHz (ns)
Parameter Abbreviation
Min
Max
Min.
Max.
T₁
Clock Rise to ADDR Valid Delay
—
7.7
—
7.7
T₂
Clock Rise to ADDR Hold Time
2.2
—
2.2
—
T₃
Clock Fall to Output DATA Valid Delay
—
6
—
6
T₄
Clock Rise to DATA Hold Time
2.3
—
2.3
—
T₅
Clock Rise to CSx Assertion Delay
2.6
10.8
2.6
10.8
T₆
Clock Rise to CSx Deassertion Delay
2.4
8.8
2.4
8.8
T₇
Clock Rise to IORQ Assertion Delay
2.6
7.0
2.6
7.0
T₈
Clock Rise to IORQ Deassertion Delay
2.3
6.3
2.3
6.3
T₉
Clock Fall to WR Assertion Delay
1.8
4.5
1.8
4.5
T₁₀
Clock Rise to WR Deassertion Delay*
1.6
4.4
1.6
4.4
WR Deassertion to ADDR Hold Time
0.4
—
0.4
—
WR Deassertion to DATA Hold Time
0.5
—
0.5
—
WR Deassertion to CSx Hold Time
1.2
—
1.2
—
WR Deassertion to IORQ Hold Time
0.5
—
0.5
—
Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to ADDR, DATA, CSx,
or IORQ. In certain applications, the deassertion of WR can be concurrent with ADDR, DATA, CSx, or MREQ
when buffering is used off-chip.
PS013012-1004
PRELIMINARY
AC Characteristics