EZ80L92MCU Datasheet, PDF (59/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
44
Port x Data Direction Registers
In conjunction with the other GPIO Control Registers, the Port x Data Direction registers,
detailed in Table 8, control the operating modes of the GPIO port pins. See Table 6 for
more information.
Table 8. Port x Data Direction Registers (PB_DDR = 009Bh, PC_DDR = 009Fh,
PD_DDR = 00A3h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Port x Alternate Register 1
In conjunction with the other GPIO Control Registers, the Port x Alternate Register 1,
detailed in Table 9, control the operating modes of the GPIO port pins. See Table 6 for
more information.
Table 9. Port x Alternate Registers 1 (PB_ALT1 = 009Ch, PC_ALT1 = 00A0h,
PD_ALT1 = 00A4h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Port x Alternate Register 2
In conjunction with the other GPIO Control Registers, the Port x Alternate Register 2,
detailed in Table 10, control the operating modes of the GPIO port pins. See Table 6 for
more information.
Table 10. Port x Alternate Registers 2 (PB_ALT2 = 009Dh, PC_ALT2 = 00A1h,
PD_ALT2 = 00A5h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
PS013012-1004
PRELIMINARY
General-Purpose Input/Output