EZ80L92MCU Datasheet, PDF (127/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
112
UART Interrupt Enable Registers
The UARTx_IER register is used to enable and disable the UART interrupts. The
UARTx_IER registers share the same I/O addresses as the UARTx_BRG_H registers. See
Table 56.
Table 56. UART Interrupt Enable Registers (UART0_IER = 00C1h, UART1_IER =
00D1h)
Bit
7
6
5
Reset
0
0
0
CPU Access
R
R
R
Note: R = Read only.; R/W = Read/Write.
4
3
2
1
0
0
0
0
0
0
R R/W R/W R/W R/W
Bit
Position
[7:4]
3
MIIE
2
LSIE
1
TIE
0
RIE
Value
0000
0
1
0
1
0
1
0
1
Description
Reserved
Modem interrupt on edge detect of status inputs is disabled.
Modem interrupt on edge detect of status inputs is enabled.
Line status interrupt is disabled.
Line status interrupt is enabled for receive data errors:
incorrect parity bit received, framing error, overrun error, or
break detection.
Transmit interrupt is disabled.
Transmit interrupt is enabled. Interrupt is generated when the
transmit FIFO/buffer is empty indicating no more bytes
available for transmission.
Receive interrupt is disabled.
Receive interrupt and receiver time-out interrupt are enabled.
Interrupt is generated if the FIFO/buffer contains data ready to
be read or if the receiver times out.
PS013012-1004
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter