EZ80L92MCU Datasheet, PDF (49/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
34
Reset
RESET Operation
The RESET controller within the eZ80L92 provides a consistent system reset (RESET)
function for all type of resets that may affect the system. There are 4 events which can
cause a RESET:
• External RESET pin assertion
• Watch-Dog Timer (WDT) time-out when configured to generate a RESET
• Real-Time Clock alarm with the eZ80^® CPU in low-power SLEEP mode
• Execution of a Debug RESET command
During RESET, an internal RESET mode timer holds the system in RESET for 257 sys-
tem clock (SCLK) cycles. The RESET mode timer begins incrementing on the next rising
edge of SCLK following deactivation of all RESET events (RESET pin, Watch-Dog
Timer, Real-Time Clock, Debugger)
Note: User must determine is 257 SCLK cycles provides sufficient time for the primary
crystal oscillator to stabilize.
RESET, via the external RESET pin, must always be executed following application of
power (V_DD ramp). Without RESET following power-up, proper operation of the
eZ80L92 cannot be guaranteed.
PS013012-1004
PRELIMINARY
Reset