EZ80L92MCU Datasheet, PDF (58/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
43
edge-triggered interrupt, writing a 1 to that pin’s Port x Data register causes a reset of the
edge-detected interrupt. The programmer must set the bit in the Port x Data register to 1
before entering either single or dual edge-triggered interrupt mode for that port pin.
When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a rising
and a falling edge on the pin cause an interrupt request to be sent to the eZ80^® CPU.
When configured for single edge-triggered interrupt mode (GPIO Mode 9), the value in
the Port x Data register determines if a positive or negative edge causes an interrupt
request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges.
GPIO Control Registers
The 12 GPIO Control Registers operate in groups of four with a set for each Port (B, C,
and D). Each GPIO port features a Port Data register, Port Data Direction register, Port
Alternate register 1, and Port Alternate register 2.
Port x Data Registers
When the port pins are configured for one of the output modes, the data written to the Port
x Data registers, detailed in Table 7, are driven on the corresponding pins. In all modes,
reading from the Port x Data registers always returns the current sampled value of the cor-
responding pins. When the port pins are configured as edge-triggered interrupt sources,
writing a 1 to the corresponding bit in the Port x Data register clears the interrupt signal
that is sent to the eZ80^® CPU. When the port pins are configured for edge-selectable inter-
rupts or level-sensitive interrupts, the value written to the Port x Data register bit selects
the interrupt edge or interrupt level. See Table 6 for more information.
Table 7. Port x Data Registers (PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h)
Bit
7
6
Reset
X
X
CPU Access
R/W R/W
Note: X = Undefined; R/W = Read/Write.
5
X
R/W
4
X
R/W
3
X
R/W
2
X
R/W
1
X
R/W
0
X
R/W
PS013012-1004
PRELIMINARY
General-Purpose Input/Output