EZ80L92MCU Datasheet, PDF (56/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
41
Writing a 1 to the Port x Data register outputs a High at the pin. Writing a 0 to the Port x
Data register results in a high-impedance output.
GPIO Mode 5. Reserved. This pin produces high-impedance output.
GPIO Mode 6. This bit enables a dual edge-triggered interrupt mode. Both a rising and a
falling edge on the pin cause an interrupt request to be sent to the eZ80^® CPU. Writing a 1
to the Port x Data register bit position resets the corresponding interrupt request. Writing a
0 produces no effect. The programmer must set the Port x Data register before entering the
edge-triggered interrupt mode.
GPIO Mode 7. For Ports B, C, and D, the port pin is configured to pass control over to the
alternate (secondary) functions assigned to the pin. For example, the alternate mode func-
tion for PC7 is RI1 and the alternate mode function for PB4 is the Timer 4 Out. When
GPIO Mode 7 is enabled, the pin output data and pin tristated control come from the alter-
nate function's data output and tristate control, respectively. The value in the Port x Data
register produces no effect on operation.
Note: Input signals are sampled by the system clock before being passed to the alternate
function input.
GPIO Mode 8. The port pin is configured for level-sensitive interrupt modes. An interrupt
request is generated when the level at the pin is the same as the level stored in the Port x
Data register. The port pin value is sampled by the system clock. The input pin must be
held at the selected interrupt level for a minimum of 2 clock periods to initiate an inter-
rupt. The interrupt request remains active as long as this condition is maintained at the
external source.
GPIO Mode 9. The port pin is configured for single edge-triggered interrupt mode. The
value in the Port x Data register determines if a positive or negative edge causes an inter-
rupt request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges. The interrupt request remains active until a 1 is writ-
ten to the corresponding interrupt request of the Port x Data register bit. Writing a 0 pro-
duces no effect on operation. The programmer must set the Port x Data register before
entering the edge-triggered interrupt mode.
A simplified block diagram of a GPIO port pin is illustrated in Figure 3.
PS013012-1004
PRELIMINARY
General-Purpose Input/Output