EZ80L92MCU Datasheet, PDF (209/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
194
Table 121. Op Code Map—Second Op Code After 0EDh
Legend _{Lower Nibble of 2nd Op Code}
Upper
Nibble
of Second
Op Code
2
4
SBC
HL,BC
Mnemonic
First Operand
Second Operand
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
IN0
B,(n)
OUT0 LEA BC, LEA BC, TST
(n),B IX+d IY+d A,B
LD BC, IN0 OUT0
(HL) C,(n) (n),C
TST
LD (HL),
A,C
BC
1
IN0
D,(n)
OUT0 LEA DE, LEA DE, TST
(n),D IX+d IY+d A,D
LD DE, IN0 OUT0
(HL) E,(n) (n),E
TST
LD(HL),
A,E
DE
2
IN0
H,(n)
OUT0 LEA HL LEA HL TST
(n),H ,IX+d ,IY+d A,H
LD HL, IN0 OUT0
(HL) L,(n) (n),L
TST
LD (HL),
A,L
HL
3
LD IY, LEA IX LEA IY TST
(HL) ,IX+d ,IY+d A,(HL)
LD IX, IN0 OUT0
(HL) A,(n) (n),A
TST
LD LD (HL),
A,A
(HL),IY IX
4
IN
B,(BC)
OUT
(BC),B
SBC
HL,BC
LD
(Mmn),
BC
NEG
RETN
IM 0
5
IN
D,(BC)
OUT
(BC),D
SBC
HL,DE
LD
(Mmn),
DE
LEA IX,
IY+d
LEA IY,
IX+d
IM 1
6
IBN
H,(C)
OUT
(BC),H
SBC
HL,HL
LD
(Mmn),
HL
TST
A,n
PEA
IX+d
PEA
IY+d
7
SBC
HL,SP
LD
(Mmn),
SP
TSTIO
n
SLP
LD
I,A
LD
A,I
RRD
IN
C,(C)
OUT
(C),C
ADC
HL,BC
LD
BC,
(Mmn)
MLT
BC
RETI
LD
R,A
IN
E,(C)
OUT
(C),E
ADC
HL,DE
LD
DE,
(Mmn)
MLT
DE
IM 2
LD
A,R
IN
L,(C)
OUT
(C),L
ADC
HL,HL
LD
HL,
(Mmn)
MLT
HL
LD
MB,A
LD A,MB
RLD
IN
A,(C)
OUT
(C),A
ADC
HL,SP
LD
SP,
(Mmn)
MLT
SP
STMIX RSMIX
8
INIM OTIM INI2
INDM OTDM IND2
9
INIMR OTIMR INI2R
INDMR OTDMR IND2R
A LDI CPI INI OUTI OUTI2
LDD CPD IND OUTD OUTD2
B LDIR CPIR INIR OTIR OTI2R
LDDR CPDR INDR OTDR OTD2R
C
INIRX OTIRX
INDRX OTDRX
D
E
F
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
PS013012-1004
PRELIMINARY
Op-Code Map