EZ80L92MCU Datasheet, PDF (176/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
161
ZDI Clock and Data Conventions
The two pins used for communication with the ZDI block are the ZDI Clock pin (ZCL)
and the ZDI Data pin (ZDA). On the eZ80L92, the ZCL pin is shared with the TCK pin
while the ZDA pin is shared with the TDI pin. The ZCL and ZDA pin functions are only
available when the On-Chip Instrumentation is disabled and the ZDI is therefore enabled.
For general data communication, the data value on the ZDA pin can change only when
ZCL is Low (0). The only exception is the ZDI START bit, which is indicated by a High-
to-Low transition (falling edge) on the ZDA pin while ZCL is High.
Data is shifted into and out of ZDI, with the most significant bit (bit 7) of each byte being
first in time, and the least significant bit (bit 0) last in time. All information is passed
between the master and the slave in 8-bit (single-byte) units. Each byte is transferred with
nine clock cycles: eight to shift the data, and the ninth for internal operations.
ZDI START Condition
All ZDI commands are preceded by the ZDI START signal, which is a High-to-Low tran-
sition of ZDA when ZCL is High. The ZDI slave on the eZ80L92 continually monitors the
ZDA and ZCL lines for the START signal and does not respond to any command until this
condition is met. The master pulls ZDA Low, with ZCL High, to indicate the beginning of
a data transfer with the ZDI block. Figures 37 and 38 illustrate a valid ZDI START signal
prior to writing and reading data, respectively. A Low-to-High transition of ZDA while the
ZCL is High produces no effect.
Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as illustrated
in Figure 37. Data is shifted out during a Read from the ZDI block on the falling edge of
ZCL as illustrated in Figure 38. When an operation is completed, the master stops during
the ninth cycle and holds the ZCL signal High.
ZDI Data In
(Write)
ZDI Data In
(Write)
ZCL
ZDA
Start Signal
Figure 37. ZDI Write Timing
PS013012-1004
PRELIMINARY
ZiLOG Debug Interface