EZ80L92MCU Datasheet, PDF (229/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
214
Table 133. GPIO Port Output Timing
Parameter Abbreviation
T₁
Clock Rise to Port Output Valid Delay
T₂
Clock Rise to Port Output Hold Time
20 MHz (ns)
Min
Max
—
9.3
2.0
—
50 MHz (ns)
Min
Max
—
9.3
2.0
—
External Bus Acknowledge Timing
Table 134 provides information about the bus acknowledge timing.
Table 134. Bus Acknowledge Timing
Parameter Abbreviation
T₁
Clock Rise to BUSACK Assertion Delay
T₂
Clock Rise to BUSACK Deassertion Delay
20 MHz (ns)
Min
Max
2.8
9.3
2.5
6.5
50 MHz (ns)
Min
Max
2.8
9.3
2.5
6.5
External System Clock Driver (PHI) Timing
Table 135 provides timing information for the PHI pin. The PHI pin allows external
peripherals to synchronize with the internal system clock driver on the eZ80L92.
Table 135. PHI System Clock Timing
Parameter Abbreviation
T₁
Clock Rise to PHI Rise
T₂
Clock Fall to PHI Fall
20 MHz (ns)
Min
Max
1.6
4.6
1.8
4.3
50 MHz (ns)
Min
Max
1.6
4.6
1.8
4.3
PS013012-1004
PRELIMINARY
AC Characteristics