EZ80L92MCU Datasheet, PDF (162/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
147
Table 78. I²C Master Receive Status Codes
Code I²C State
MCU Response
Next I²C Action
48h
Addr + R
For a 7-bit address:
Transmit repeated
transmitted, ACK Set STA, clear IFLG
START
not received
Or set STP, clear IFLG
Transmit STOP
Or set STA & STP,
clear IFLG
Transmit STOP then
START
For a 10-bit address:
Write extended address
byte to DATA, clear IFLG
Transmit extended
address byte
38h
Arbitration lost
Clear IFLG
Return to idle
Or set STA, clear IFLG
Transmit START when
bus is free
68h
Arbitration lost,
Clear IFLG, clear AAK = 0 Receive data byte,
SLA+W received,
transmit NACK
ACK transmitted _{Or clear IFLG, set AAK = 1 Receive data byte,}
transmit ACK
78h
Arbitration lost,
Same as code 68h
General call addr
received, ACK
transmitted
Same as code 68h
B0h
Arbitration lost,
Write byte to DATA,
Transmit last byte,
SLA+R received, clear IFLG, clear AAK = 0 receive ACK
ACK transmitted _{Or write byte to DATA,}
Transmit data byte,
clear IFLG, set AAK = 1 receive ACK
Note: R = Read bit; in essence, the lsb is set to 1.
If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address
plus the Write bit. The master then issues a restart followed by the first part of the 10-bit
address again, but with the Read bit. The status code then becomes 40h or 48h. It is the
responsibility of the slave to remember that it had been selected prior to the restart.
If a repeated START condition is received, the status code is 10h instead of 08h.
After each data byte is received, the IFLG is set and one of the status codes listed in Table
79 is in the I2C_SR register.
PS013012-1004
PRELIMINARY
I²C Serial I/O Interface