EZ80L92MCU Datasheet, PDF (26/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
11
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued)
Pin #
47
48
49
50
51
52
53
54
55
Symbol Function
Signal Direction
Description
RD
Read
Output, Active Low
RD Low indicates that the eZ80L92 MCU is
reading from the current address location.
This pin is tristated during bus
acknowledge cycles.
WR
Write
Output, Active Low
WR indicates that the CPU is writing to the
current address location. This pin is
tristated during bus acknowledge cycles.
INSTRD
Instruction Output, Active Low
Read Indicator
INSTRD (with MREQ and RD) indicates
the eZ80L92 MCU is fetching an instruction
from memory. This pin is tristated during
bus acknowledge cycles.
WAIT
WAIT Request Input, Active Low
Driving the WAIT pin Low forces the CPU
to wait additional clock cycles for an
external peripheral or external memory to
complete its Read or Write operation.
RESET
Reset
Schmitt Trigger Input, This signal is used to initialize the eZ80L92
Active Low
MCU. This input must be Low for a
minimum of 3 system clock cycles, and
must be held Low until the clock is stable.
This input includes a Schmitt trigger to
allow RC rise times.
NMI
Nonmaskable Schmitt Trigger Input, The NMI input is a higher priority input than
Interrupt
Active Low
the maskable interrupts. It is always
recognized at the end of an instruction,
regardless of the state of the interrupt
enable control bits. This input includes a
Schmitt trigger to allow RC rise times.
BUSREQ Bus Request Input, Active Low
External devices can request the eZ80L92
MCU to release the memory interface bus
for their use, by driving this pin Low.
BUSACK
Bus
Output, Active Low
Acknowledge
The eZ80L92 MCU responds to a Low on
BUSREQ, by tristating the address, data,
and control signals, and by driving the
BUSACK line Low. During bus
acknowledge cycles ADDR[23:0], IORQ,
and MREQ are inputs.
HALT_SLP HALT and
SLEEP
Indicator
Output, Active Low
A Low on this pin indicates that the CPU
has entered either HALT or SLEEP mode
because of execution of either a HALT or
SLP instruction.
PS013012-1004
PRELIMINARY
Architectural Overview