EZ80L92MCU Datasheet, PDF (50/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
35
Low-Power Modes
Overview
The eZ80L92 provides a range of power-saving features. The highest level of power
reduction is provided by SLEEP mode. The next level of power reduction is provided by
the HALT instruction. The lowest level of power reduction is provided by the clock
peripheral power-down registers.
SLEEP Mode
Execution of the eZ80^® CPU’s SLP instruction places the eZ80L92 into SLEEP mode. In
SLEEP mode, the operating characteristics are:
• Primary crystal oscillator is disabled
• System clock is disabled
• eZ80^® CPU is idle
• Program counter (PC) stops incrementing
• 32KHz crystal oscillator continues to operate and drive the Real-Time Clock and the
Watch-Dog Timer (if WDT is configured to operate from the 32 KHz oscillator)
The eZ80^® CPU can be brought out of SLEEP mode by any of the following operations:
• RESET via the external RESET pin driven Low
• RESET via a Real-Time Clock alarm
• RESET via a Watch-Dog Timer time-out (if running off of the 32KHz oscillator and
configured to generate a RESET upon time-out)
• RESET via execution of a Debug RESET command
After exiting SLEEP mode, the standard RESET delay occurs to allow the primary crystal
oscillator to stabilize. Refer to the Reset section 34 for more information.
HALT Mode
Execution of the eZ80^® CPU’s HALT instruction places the eZ80L92 into HALT mode. In
HALT mode, the operating characteristics are:
• Primary crystal oscillator is enabled and continues to operate
• System clock is enabled and continues to operate
PS013012-1004
PRELIMINARY
Low-Power Modes