EZ80L92MCU Datasheet, PDF (68/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
53
generate Chip Select signals in response to the address on the bus. External devices cannot
access the internal registers of the eZ80L92.
Bus Mode Controller
The bus mode controller allows the address and data bus timing and signal formats of the
eZ80L92 to be configured to connect seamlessly with external eZ80^®, Z80-, Intel-, or
Motorola-compatible devices. Bus modes for each of the chip selects can be configured
independently using the Chip Select Bus Mode Control Registers. The number of eZ80^®
system clock cycles per bus mode state is also independently programmable. For Intel bus
mode, multiplexed address and data can be selected in which the lower byte of the address
and the data byte both use the data bus, DATA[7:0]. Each of the bus modes is explained in
more detail in the following sections.
eZ80 Bus Mode
Chip selects configured for eZ80 Bus Mode do not modify the bus signals from the CPU.
The timing diagrams for external Memory and I/O Read and Write operations are shown
in the AC Characteristics section on page 204. The default mode for each chip select is
eZ80 mode.
Z80 Bus Mode
Chip selects configured for Z80 mode modify the eZ80^® bus signals to match the Z80
microprocessor address and data bus interface signal format and timing. During Read
operations, the Z80 Bus Mode employs three states (T1, T2, and T3) as described in Table
14.
Table 14. Z80 Bus Mode Read States
STATE T1
STATE T2
STATE T3
The Read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated Chip Select signal is asserted.
During State T2, the RD signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one
eZ80^® system clock cycle prior to the end of State T2, additional WAIT states (T_WAIT) are
asserted until the WAIT pin is driven High.
During State T3, no bus signals are altered. The data is latched by the eZ80L92 at the
rising edge of the eZ80^® system clock at the end of State T3.
During Write operations, Z80 Bus Mode employs 3 states (T1, T2, and T3) as described in
Table 15.
PS013012-1004
PRELIMINARY
Chip Selects and Wait States