EZ80L92MCU Datasheet, PDF (226/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
211
Wait State Timing for Read Operations
Figure 53 illustrates the extension of the memory access signals using a single WAIT state
for a Read operation. This WAIT state is generated by setting CS_WAIT to 001 in the
Chip Select Control Register.
X _IN
ADDR[23:0]
DATA[7:0]
(input)
T_CLK
T_{CSx_WAIT}
T_WAIT
CSx
MREQ
RD
INSTRD
Figure 53. Wait State Timing for Read Operations
PS013012-1004
PRELIMINARY
AC Characteristics