EZ80L92MCU Datasheet, PDF (197/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
182
ZDI Bus Status Register
The ZDI Bus Status register monitors BUSACKs during DEBUG mode. See Table 105.
Table 105. ZDI Bus Control Register (ZDI_BUS_STAT = 17h in the ZDI Register
Read-Only Address Space)
Bit
Reset
CPU Access
Note: R = Read-Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
7
ZDI_BUSAcK_En
6
ZDI_BUS_STAT
[5:0]
Value
0
1
0
1
000000
Description
Bus requests by external peripherals using the
BUSREQ pin are ignored. The bus acknowledge
signal, BUSACK, is not asserted.
Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK
pin.
Address and data buses are not relinquished to an
external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
Reserved.
PS013012-1004
PRELIMINARY
ZiLOG Debug Interface