EZ80L92MCU Datasheet, PDF (57/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
42
GPIO Register
Data (Input)
QD
QD
System Clock
Mode 1
Mode 4
Data Bus D Q
System Clock
GPIO Register
Data (Output)
Mode 1
Mode 3
Figure 3. GPIO Port Pin Block Diagram
V_DD
Port
Pin
GND
GPIO Interrupts
Each port pin can be used as an interrupt source. Interrupts can be either level- or edge-
triggered.
Level-Triggered Interrupts
When the port is configured for level-triggered interrupts, the corresponding port pin is
tristated. An interrupt request is generated when the level at the pin is the same as the level
stored in the Port x Data register. The port pin value is sampled by the system clock. The
input pin must be held at the selected interrupt level for a minimum of 2 consecutive clock
cycles to initiate an interrupt. The interrupt request remains active as long as this condition
is maintained at the external source.
For example, if PD3 is programmed for low-level interrupt and the pin is forced Low for 2
consecutive clock cycles, an interrupt request signal is generated from that port pin and
sent to the eZ80^® CPU. The interrupt request signal remains active until the external
device driving PD3 forces the pin High.
Edge-Triggered Interrupts
When the port is configured for edge-triggered interrupts, the corresponding port pin is
tristated. If the pin receives the correct edge from an external device, the port pin gener-
ates an interrupt request signal to the eZ80^® CPU. Any time a port pin is configured for
PS013012-1004
PRELIMINARY
General-Purpose Input/Output