EZ80L92MCU Datasheet, PDF (200/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
185
OCI Interface
There are five dedicated pins on the eZ80L92 for the OCI interface. Four (TCK, TMS,
TDI, and TDO) are required for IEEE Standard 1149.1-compatible JTAG ports. The TRI-
GOUT pin provides additional testability features. These five OCI pins are described in
Table 107.
Table 107. OCI Pins
Symbol
TCK
TMS
TDI
TDO
TRIGOUT
Name
Clock.
Test Mode Select
Data In
Data Out
Trigger Output
Type
Input
Input
Input
(OCI enabled)
I/O
(OCI disabled)
Output
Output
Description
Asynchronous to the primary eZ80L92 system clock.
The TCK period but must be at least twice the
system clock period. During RESET, this pin is
sampled to select either OCI or ZDI DEBUG modes.
If Low during RESET, the OCI is enabled. If High
during RESET, the OCI is powered down and ZDI
DEBUG mode is enabled. When ZDI DEBUG mode
is active, this pin is the ZDI clock. On-chip pull-up
ensures a default value of 1 (High).
This serial test mode input controls JTAG mode
selection. On-chip pull-up ensures a default value of
1 (High). The TMS signal is sampled on the rising
edge of the TCK signal.
Serial test data input. On-chip pull-up ensures a
default value of 1 (High). This pin is input-only when
the OCI is enabled. The input data is sampled on the
rising edge of the TCK signal.
When the OCI is disabled, this pin functions as the
ZDA (ZDI Data) I/O pin.
The output data changes on the falling edge of the
TCK signal.
Generates an active High trigger pulse when valid
OCI trigger events occur. Output is tristate when no
data is being driven out.
PS013012-1004
PRELIMINARY
On-Chip Instrumentation