EZ80L92MCU Datasheet, PDF (65/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
50
Table 13. Register Values for Memory Chip Select Example in Figure 4
Chip CSx_CTL[3] CSx_CTL[4]
Select CSx_EN
CSx_IO CSx_LBR CSx_UBR Description
CS0
1
0
00h
7Fh CS0 is enabled as a Memory Chip Select.
Valid addresses range from 000000h–
7FFFFFh.
CS1
1
0
00h
9Fh CS1 is enabled as a Memory Chip Select.
Valid addresses range from 800000h–
9FFFFFh.
CS2
1
0
A0h
CFh CS2 is enabled as a Memory Chip Select.
Valid addresses range from A00000h–
CFFFFFh.
CS3
1
0
D0h
FFh CS3 is enabled as a Memory Chip Select.
Valid addresses range from D00000h–
FFFFFFh.
I/O Chip Select Operation
I/O Chip Selects can only be active when the CPU is performing I/O instructions. Because
the I/O space is separate from the memory space in the eZ80L92 device, there can never
be a conflict between I/O and memory addresses.
The eZ80L92 supports a 16-bit I/O address. The I/O Chip Select logic decodes the High
byte of the I/O address, ADDR[15:8]. Because the upper byte of the address bus,
ADDR[23:16], is ignored, the I/O devices can always be accessed from within any mem-
ory mode (ADL or Z80). The MBASE offset value used for setting the Z80 MEMORY
mode page is also always ignored.
Four I/O Chip Selects are available with the eZ80L92. To generate a particular I/O Chip
Select, the following conditions must be met:
• The Chip Select is enabled by setting CSX_EN to 1
• The Chip Select is configured for I/O by setting CSx_IO to 1
• An I/O Chip Select address match occurs—ADDR[15:8] = CSx_LBR[7:0]
• No higher-priority (lower-number) Chip Select meets the above conditions
• The I/O address is not within the on-chip peripheral address range 0080h–00FFh. On-
chip peripheral registers assume priority for all addresses where:
0080h ≤ ADDR[15:0] ≤ 00FFh
• An I/O instruction must be executing
PS013012-1004
PRELIMINARY
Chip Selects and Wait States