EZ80L92MCU Datasheet, PDF (40/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
25
Register Map
All on-chip peripheral registers are accessed in the I/O address space. All I/O operations
employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all
I/O operations (ADDR[23:16] = UU). All I/O operations using 16-bit addresses within the
range 0080h–00FFh are routed to the on-chip peripherals. External I/O Chip Selects are
not generated if the address space programmed for the I/O Chip Selects overlaps the
0080h–00FFh address range.
Registers at unused addresses within the 0080h–00FFh range assigned to on-chip periph-
erals are not implemented. Read access to such addresses returns unpredictable values and
Write access produces no effect. Table 3 diagrams the register map for the eZ80L92.
Table 3. Register Map
Address
(hex) Mnemonic
Name
Reset
(hex)
CPU Page
Access #
Programmable Reload Counter/Timers
0080 TMR0_CTL
Timer 0 Control Register
00
R/W
81
0081 TMR0_DR_L Timer 0 Data Register—Low Byte
00
R
82
TMR0_RR_L Timer 0 Reload Register—Low Byte
00
W
84
0082 TMR0_DR_H Timer 0 Data Register—High Byte
00
R
83
TMR0_RR_H Timer 0 Reload Register—High Byte
00
W
85
0083 TMR1_CTL
Timer 1 Control Register
00
R/W
81
0084 TMR1_DR_L Timer 1 Data Register—Low Byte
00
R
82
TMR1_RR_L Timer 1 Reload Register—Low Byte
00
W
84
0085 TMR1_DR_H Timer 1 Data Register—High Byte
00
R
83
TMR1_RR_H Timer 1 Reload Register—High Byte
00
W
85
0086 TMR2_CTL
Timer 2 Control Register
00
R/W
81
Notes:
1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-
out reset, the Watch-Dog Timer Control register is reset to 20h.
2. When the CPU reads this register, the current sampled value of the port is read.
3. Read-only if RTC is locked; Read/Write if RTC is unlocked.
4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm
Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
PS013012-1004
PRELIMINARY
Register Map