EZ80L92MCU Datasheet, PDF (173/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
158
ble clock divider stages, a high sampling frequency can be ensured while allowing the
MASTER mode output to be set to a lower frequency.
Bus Clock Speed
The I²C bus is defined for bus clock speeds up to 100 Kbps (400 Kbps in FAST mode).
To ensure correct detection of START and STOP conditions on the bus, the I²C must sam-
ple the I²C bus at least ten times faster than the bus clock speed of the fastest master on the
bus. The sampling frequency should therefore be at least 1 MHz (4 MHz in FAST mode)
to guarantee correct operation with other bus masters.
The I²C sampling frequency is determined by the frequency of the eZ80L92 system clock
and the value in the I2C_CCR bits 2 to 0. The bus clock speed generated by the I²C in
MASTER mode is determined by the frequency of the input clock and the values in
I2C_CCR[2:0] and I2C_CCR[6:3].
I²C Software Reset Register
The I2C_SRR register is a Write-Only register. Writing any value to this register performs
a software reset of the I²C module. See Table 88.
Table 88. I²C Software Reset Register (I2C_SRR = 00CDh)
Bit
7
6
5
4
3
2
1
0
Reset
X
X
X
X
X
X
X
X
CPU Access
W
W
W
W
W
W
W
W
Note: W = Write-Only.
Bit
Position
[7:0]
SRR
Value Description
00h– Writing any value to this register performs a software reset of
FFh the I²C module.
PS013012-1004
PRELIMINARY
I²C Serial I/O Interface