EZ80L92MCU Datasheet, PDF (66/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
51
If all of the foregoing conditions are met to generate an I/O Chip Select, then the follow-
ing actions occur:
• The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low)
• IORQ is asserted (driven Low)
• Depending upon the instruction, either RD or WR is asserted (driven Low)
WAIT States
For each of the Chip Selects, programmable WAIT states can be asserted to provide exter-
nal devices with additional clock cycles to complete their Read or Write operations. The
number of WAIT states for a particular Chip Select is controlled by the 3-bit field
CSx_WAIT (CSx_CTL[7:5]). The WAIT states can be independently programmed to pro-
vide 0 to 7 WAIT states for each Chip Select. The WAIT states idle the CPU for the speci-
fied number of system clock cycles.
WAIT Input Signal
Similar to the programmable WAIT states, an external peripheral can drive the WAIT
input pin to force the CPU to provide additional clock cycles to complete its Read or Write
operation. Driving the WAIT pin Low stalls the CPU. The CPU resumes operation on the
first rising edge of the internal system clock following deassertion of the WAIT pin.
Caution:
If the WAIT pin is to be driven by an external device, the corresponding Chip
Select for the device must be programmed to provide at least one WAIT state.
Due to input sampling of the WAIT input pin (shown in Figure 5), one pro-
grammable WAIT state is required to allow the external peripheral sufficient
time to assert the WAIT pin. It is recommended that the corresponding Chip
Select for the external device be programmed to provide the maximum num-
ber of WAIT states (seven).
Wait
Pin
DQ
eZ80
CPU
System Clock
Figure 5. Wait Input Sampling Block Diagram
PS013012-1004
PRELIMINARY
Chip Selects and Wait States