EZ80L92MCU Datasheet, PDF (70/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
55
System Clock
ADDR[23:0]
T1
T2
T_CLK
T3
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
Figure 8. Z80 Bus Mode Write Timing Example
Intel Bus Mode
Chip selects configured for Intel Bus Mode modify the eZ80^® bus signals to duplicate a
four-state memory transfer similar to that found on Intel-style microprocessors. The bus
signals and eZ80L92 pins are mapped as illustrated in Figure 9. In Intel Bus Mode, the
user can select either multiplexed or nonmultiplexed address and data buses. In nonmulti-
plexed operation, the address and data buses are separate. In multiplexed operation, the
lower byte of the address, ADDR[7:0], also appears on the data bus, DATA[7:0], during
State T1 of the Intel Bus Mode cycle. During multiplexed operation, the lower byte of the
address bus also appears on the address bus in addition to the data bus.
PS013012-1004
PRELIMINARY
Chip Selects and Wait States