EZ80L92MCU Datasheet, PDF (78/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
63
eZ80 Bus Mode
Signals (Pins)
INSTRD
RD
WR
WAIT
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Bus Mode
Controller
Motorola Bus
Signal Equvalents
AS
DS
R/W
DTACK
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Figure 14. Motorola Bus Mode Signal and Pin Mapping
During Write operations, the Motorola Bus Mode employs 8 states (S0, S1, S2, S3, S4, S5,
S6, and S7) as described in Table 20.
Table 20. Motorola Bus Mode Read States
STATE S0 The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle.
STATE S1 Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].
STATE S2 On the rising edge of state S2, the CPU asserts AS and DS.
STATE S3 During state S3, no bus signals are altered.
STATE S4
During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral
signal. If the termination signal is not asserted at least one full CPU clock period prior to
the rising clock edge at the end of S4, the CPU inserts WAIT (T_WAIT) states until DTACK is
asserted. Each WAIT state is a full bus mode cycle.
STATE S5 During state S5, no bus signals are altered.
PS013012-1004
PRELIMINARY
Chip Selects and Wait States