EZ80L92MCU Datasheet, PDF (84/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
69
Chip Select x Control Registers
The Chip Select x Control register, detailed in Table 24, enables the Chip Selects, specifies
the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip
Select 0 Control register is E8h, while the reset state for the 3 other Chip Select control
registers is 00h.
Table 24. Chip Select x Control Registers (CS0_CTL = 00AAh, CS1_CTL = 00ADh,
CS2_CTL = 00B0h, CS3_CTL = 00B3h)
Bit
7
6
5
4
3
2
1
0
CS0_CTL Reset
1
1
1
0
1
0
0
0
CS1_CTL Reset
0
0
0
0
0
0
0
0
CS2_CTL Reset
0
0
0
0
0
0
0
0
CS3_CTL Reset
0
0
0
0
0
0
0
0
CPU Access
R/W R/W R/W R/W R/W R
R
R
Note: R/W = Read/Write; R = Read Only.
Bit
Position
Value Description
[7:5]
CSx_WAIT*
000 0 WAIT states are asserted when this Chip Select is active.
001 1 WAIT state is asserted when this Chip Select is active.
010 2 WAIT states are asserted when this Chip Select is active.
011 3 WAIT states are asserted when this Chip Select is active.
100 4 WAIT states are asserted when this Chip Select is active.
101 5 WAIT states are asserted when this Chip Select is active.
110 6 WAIT states are asserted when this Chip Select is active.
111 7 WAIT states are asserted when this Chip Select is active.
4
CSx_IO
0
Chip Select is configured as a Memory Chip Select.
1
Chip Select is configured as an I/O Chip Select.
3
CSx_EN
0
Chip Select is disabled.
1
Chip Select is enabled.
[2:0]
000 Reserved.
Note: *These WAIT state settings apply only to the default eZ80 bus mode. See Table 25.
PS013012-1004
PRELIMINARY
Chip Selects and Wait States