EZ80L92MCU Datasheet, PDF (53/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
38
Table 5. Clock Peripheral Power-Down Register 2 (CLK_PPD2 = 00DCh)
Bit
7
6
Reset
0
0
CPU Access
R/W R
Note: R/W = Read/Write; R = Read Only.
5
4
3
2
1
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W
Bit
Position
7
PHI_OFF
6
5
PRT5_OFF
4
PRT4_OFF
3
PRT3_OFF
2
PRT2_OFF
1
PRT1_OFF
0
PRT0_OFF
Value Description
1
PHI Clock output is disabled (output is high-impedance).
0
PHI Clock output is enabled.
0
Reserved.
1
System clock to PRT5 is powered down.
0
System clock to PRT5 is powered up.
1
System clock to PRT4 is powered down.
0
System clock to PRT4 is powered up.
1
System clock to PRT3 is powered down.
0
System clock to PRT3 is powered up.
1
System clock to PRT2 is powered down.
0
System clock to PRT2 is powered up.
1
System clock to PRT1 is powered down.
0
System clock to PRT1 is powered up.
1
System clock to PRT0 is powered down.
0
System clock to PRT0 is powered up.
PS013012-1004
PRELIMINARY
Low-Power Modes