EZ80L92MCU Datasheet, PDF (167/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
152
I²C Data Register
This register contains the data byte/slave address to be transmitted or the data byte just
received. In transmit mode, the most significant bit of the byte is transmitted first. In
receive mode, the first bit received is placed in the most significant bit of the register.
After each byte is transmitted, the I2C_DR register contains the byte that is present on the
bus in case a lost arbitration event occurs. See Table 83.
Table 83. I²C Data Register (I2C_DR = 00CAh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:0]
DATA
Value Description
00h– I²C data byte.
FFh
I²C Control Register
The I2C_CTL register is a control register that is used to control the interrupts and the
master slave relationships on the I²C bus.
When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when the
IFLG is set to 1. When IEN is cleared to 0, the interrupt line always remains Low.
When the Bus Enable bit (ENAB) is set to 0, the I²C bus inputs SCLx and SDAx are
ignored and the I²C module does not respond to any address on the bus. When ENAB is
set to 1, the I²C responds to calls to its slave address and to the general call address if the
GCE bit (I2C_SAR[0]) is set to 1.
When the Master Mode Start bit (STA) is set to 1, the I²C enters MASTER mode and
sends a START condition on the bus when the bus is free. If the STA bit is set to 1 when
the I²C module is already in MASTER mode and one or more bytes are transmitted, then a
repeated START condition is sent. If the STA bit is set to 1 when the I²C block is being
accessed in SLAVE mode, the I²C completes the data transfer in SLAVE mode and then
enters MASTER mode when the bus is released. The STA bit is automatically cleared
after a START condition is set. Writing a 0 to this bit produces no effect.
If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition is
transmitted on the I²C bus. If the STP bit is set to 1 in slave move, the I²C module oper-
ates as if a STOP condition is received, but no STOP condition is transmitted. If both STA
and STP bits are set, the I²C block first transmits the STOP condition (if in MASTER
PS013012-1004
PRELIMINARY
I²C Serial I/O Interface