EZ80L92MCU Datasheet, PDF (20/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
5
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device
Pin # Symbol
1
ADDR0
Function
Signal Direction
Address Bus Bidirectional
2
ADDR1 Address Bus Bidirectional
3
ADDR2 Address Bus Bidirectional
4
ADDR3 Address Bus Bidirectional
5
ADDR4 Address Bus Bidirectional
6
ADDR5 Address Bus Bidirectional
Description
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be read
or written. Configured as an input during
bus acknowledge cycles. Drives the Chip
Select/Wait State Generator block to
generate Chip Selects.
PS013012-1004
PRELIMINARY
Architectural Overview