EZ80L92MCU Datasheet, PDF (170/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
155
I²C Status Register
The I2C_SR register is a Read-Only register that contains a 5-bit status code in the five
most significant bits: the three least significant bits are always 0. The Read-Only I2C_SR
registers share the same I/O addresses as the Write-Only I2C_CCR registers. See Table
85.
Table 85. I²C Status Registers (I2C_SR = 00CCh)
Bit
Reset
CPU Access
Note: R = Read only.
7
6
5
4
3
2
1
0
1
1
1
1
1
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
[7:3]
STAT
[2:0]
Value
00000–
11111
000
Description
5-bit I²C status code.
Reserved.
There are 29 possible status codes, as listed in Table 86. When the I2C_SR register con-
tains the status code F8h, no relevant status information is available, no interrupt is gener-
ated and the IFLG bit in the I2C_CTL register is not set. All other status codes correspond
to a defined state of the I²C.
When each of these states is entered, the corresponding status code appears in this register
and the IFLG bit in the I2C_CTL register is set. When the IFLG bit is cleared, the status
code returns to F8h.
Table 86. I²C Status Codes
Code
00h
08h
10h
18h
20h
28h
30h
38h
Status
Bus error
START condition transmitted
Repeated START condition transmitted
Address and Write bit transmitted, ACK received
Address and Write bit transmitted, ACK not received
Data byte transmitted in MASTER mode, ACK received
Data byte transmitted in MASTER mode, ACK not received
Arbitration lost in address or data byte
PS013012-1004
PRELIMINARY
I²C Serial I/O Interface