EZ80L92MCU Datasheet, PDF (191/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
176
ZDI Bus Control Register
The ZDI Bus Control register controls bus requests during DEBUG mode. It enables or
disables bus acknowledge in ZDI DEBUG mode and allows ZDI to force assertion of the
BUSACK signal. This register should only be written during ZDI Debug mode (that is,
following a BREAK). See Table 97.
Table 97. ZDI Bus Control Register (ZDI_BUS_CTL = 17h in the ZDI Register Write-
Only Address Space)
Bit
Reset
CPU Access
Note: W = Write-only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Bit
Position
7
ZDI_BUSAK_EN
6
ZDI_BUSAK
[5:0]
Value Description
0
Bus requests by external peripherals using the BUSREQ
pin are ignored. The bus acknowledge signal, BUSACK,
is not asserted in response to any bus requests.
1
Bus requests by external peripherals using the BUSREQ
pin are accepted. A bus acknowledge occurs at the end of
the current ZDI operation. The bus acknowledge is
indicated by asserting the BUSACK pin in response to a
bus request.
0
Deassert the bus acknowledge pin (BUSACK) to return
control of the address and data buses back to ZDI.
1
Assert the bus acknowledge pin (BUSACK) to pass
control of the address and data buses to an external
peripheral.
000000 Reserved.
PS013012-1004
PRELIMINARY
ZiLOG Debug Interface