EZ80L92MCU Datasheet, PDF (67/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
52
An example of WAIT state operation is illustrated in Figure 6. In this example, the Chip
Select is configured to provide a single WAIT state. The external peripheral being
accessed drives the WAIT pin Low to request assertion of an additional WAIT state. If the
WAIT pin is asserted for additional system clock cycles, WAIT states are added until the
WAIT pin is deasserted (High).
T_CLK
T_{CSx_WAIT}
T_WAIT
X _IN
ADDR[23:0]
DATA[7:0]
(input)
CSx
MREQ
RD
INSTRD
WAIT
Figure 6. Wait State Operation Example (Read Operation)
Chip Selects During Bus Request/Bus Acknowledge Cycles
When the CPU relinquishes the address bus to an external peripheral in response to an
external bus request (BUSREQ), it drives the bus acknowledge pin (BUSACK) Low. The
external peripheral can then drive the address bus (and data bus). The CPU continues to
PS013012-1004
PRELIMINARY
Chip Selects and Wait States