EZ80L92MCU Datasheet, PDF (235/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
220
CONTINUOUS mode 78
CPHA—see clock phase
CPOL—see clock polarity bit
CS0 9, 21, 48–51
CS1 9, 21, 48–51
CS2 9, 21, 48, 50–51
CS3 9, 21, 48, 50–51
CTS—see Clear to Send
CTS0 14, 124
CTS1 16
Customer Feedback Form 226
Customer Information 226
cycle termination signal 63–64
D
data bus 9–10, 52–53, 55–57, 60, 64, 70, 90, 166,
176, 182
Data Carrier Detect 14, 17, 117, 120
Delta Status Change Of 120
Data Set Ready 14, 16, 117, 120
Delta Status Change Of 120
Data Terminal Ready 14, 16, 117, 120
Data Transfer Procedure with SPI configured as a
Slave 132
Data Transfer Procedure with SPI Configured as
the Master 132
data transfer, SPI 135
Data Validity 139
DATA0 9, 21
DATA1 9, 22
DATA2 10, 22
DATA3 10, 22
DATA4 10, 22
DATA5 10, 22
DATA6 10, 22
DATA7 10, 22
DC Characteristics 202
DCD—see Data Carrier Detect
DCD0 14, 124
DCD1 17
DCTS—see Clear to Send, Delta Status Change Of
DDCD—see Data Carrier Detect, Delta Status
Change Of
DDSR—see Data Set Ready, Delta Status Change
Of
Document Information 218
Document Number Description 218
DSR—see Data Set Ready
DSR0 14, 124
DSR1 16
DTACK—see cycle termination signal
DTR—see Data Terminal Ready
DTR0 14, 124
DTR1 16
E
Edge-Triggered Interrupts 42
EI—see Interrupt Enable
Electrical Characteristics 201
Enabling and Disabling the WDT 73
endec—seeInfrared Data Association encoder/
decoder
Event Counter 79
External Bus Acknowledge Timing 214
External I/O Read Timing 208
External I/O Write Timing 209
External Memory Read Timing 205
External Memory Write Timing 206
External System Clock Driver (PHI) Timing 214
eZ80 CPU 34–36, 51–52, 56–57, 63–64, 122, 168,
184
eZ80 CPU Core 32
eZ80 CPU Instruction Set 187
eZ80 Product ID Low and High Byte Registers 179
eZ80 Product ID Revision Register 180
F
FAST mode 138, 158
Features 1
eZ80 CPU Core 32
full-duplex transmission 130
Functional Description, Infrared Encoder/Decoder
122
PS013012-1004
PRELIMINARY
Index