EZ80L92MCU Datasheet, PDF (54/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
39
General-Purpose Input/Output
GPIO Overview
The eZ80L92 features 24 General-Purpose Input/Output (GPIO) pins. The GPIO pins are
assembled as three 8-bit ports— Port B, Port C, and Port D. All port signals can be config-
ured for use as either inputs or outputs. In addition, all of the port pins can be used as vec-
tored interrupt sources for the eZ80^® CPU.
GPIO Operation
The GPIO operation is the same for all 3 GPIO ports (Ports B, C, and D). Each port fea-
tures eight GPIO port pins. The operating mode for each pin is controlled by four bits that
are divided between four 8-bit registers. These GPIO mode control registers are:
• Port x Data Register (Px_DR)
• Port x Data Direction Register (Px_DDR)
• Port x Alternate Register 1 (Px_ALT1)
• Port x Alternate Register 2 (Px_ALT2)
where x can be B, C, or D representing any of the three GPIO ports B, C, or D. The mode
for each pin is controlled by setting each register bit pertinent to the pin to be configured.
For example, the operating mode for Port B Pin 7 (PB7), is set by the values contained in
PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7].
The combination of the GPIO control register bits allows individual configuration of each
port pin for nine modes. In all modes, reading of the Port x Data register returns the sam-
pled state, or level, of the signal on the corresponding pin. Table 6 indicates the function of
each port signal based upon these four register bits. After a RESET event, all GPIO port
pins are configured as standard digital inputs, with interrupts disabled.
PS013012-1004
PRELIMINARY
General-Purpose Input/Output