EZ80L92MCU Datasheet, PDF (133/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
118
UART Line Status Registers
This register is used to show the status of UART interrupts and registers. See Table 63.
Table 63. UART Line Status Registers (UART0_LSR = 00C5h, UART1_LSR = 00 D5h)
Bit
Reset
CPU Access
Note: R = Read only.
7
6
5
4
3
2
1
0
0
1
1
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
7
ERR
6
TEMT
5
THRE
4
BI
Value
0
1
0
1
0
1
0
1
Description
Always 0 when operating with the FIFO disabled. With the
FIFO enabled, this bit is reset when the UARTx_LSR register
is read and there are no more bytes with error status in the
FIFO.
Error detected in the FIFO. There is at least 1 parity, framing
or break indication error in the FIFO.
Transmit holding register/FIFO is not empty or transmit shift
register is not empty or transmitter is not idle.
Transmit holding register/FIFO and transmit shift register are
empty; and the transmitter is idle. This bit cannot be set to 1
during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.
Transmit holding register/FIFO is not empty.
Transmit holding register/FIFO is empty. This bit cannot be
set to 1 during the BREAK condition. This bit only becomes 1
after the BREAK command is removed.
Receiver does not detect a BREAK condition. This bit is reset
to 0 when the UARTx_LSR register is read.
Receiver detects a BREAK condition on the receive input line.
This bit is 1 if the duration of BREAK condition on the receive
data is longer than one character transmission time, the time
depends on the programming of the UARTx_LSR register. In
case of FIFO only one null character is loaded into the
receiver FIFO with the framing error. The framing error is
revealed to the eZ80^® whenever that particular data is read
from the receiver FIFO.
PS013012-1004
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter